SH7724

• Renesas Electronics original architecture (SH-4A)
• 32-bit internal data bus
• General register file
• RISC-type instruction set (upward compatible with the SH-1, SH-2, SH-3, and SH-4)
• Superscalar architecture (providing simultaneous execution of two instructions) including FPU
• Instruction execution time: Up to two instructions/cycle
• Virtual address space: 4 Gbytes
• Space identifier ASIDs: 8 bits, 256 virtual address spaces
• Internal multiplier
• Eight-stage pipeline

• On-chip floating-point coprocessor
• Supports single precision (32 bits) and double precision (64 bits)
• Supports IEEE754-compliant data types and exceptions
• Rounding modes: Round to Nearest and Round to Zero
• Handling of denormalized numbers: Truncation to zero or interrupt generation for compliance with IEEE754
• Floating-point registers: 32 bits x16 words x2 banks
  (single-precision x16 registers or double-precision x8 registers) x2 banks
• 32-bit CPU-FPU floating-point communication register (FPUL)
• Supports FMAC (multiply-and-accumulate) instruction
• Supports FDIV (divide) and FSQRT (square root) instructions
• Supports FLDI0/FLDI1 (load constant 0/1) instructions
• 3D graphics instructions (single-precision only)
• 10-stage pipeline

• 4-Gbyte address space, 256 address areas (8-bit ASIDs)
• Single-virtual-memory mode and multiple-virtual-memory mode
• Supports multiple page sizes: 1 Kbyte, 4 Kbytes, 8 Kbytes, 64 Kbytes, 256 Kbytes, 1 Mbyte, 4 Mbytes, and 64 Mbytes
• 4-entry fully-associative TLB for instructions
• 64-entry fully-associative TLB for instructions and operands
• Supports software-controlled replacement and random-counter replacement algorithm
• TLB contents can be accessed directly by address mapping
• Supports 32-bit physical address expansion mode
  Note: The 29-bit physical address mode is selected in the initial state.

• Instruction cache (IC)
  • 32-Kbyte, 4-way set associative
  • 32-byte block length
• Operand cache (OC)
  • 32-Kbyte, 4-way set associative
  • 32-byte block length
  • Selectable write mode (copy-back or write-through)
• Store queue (32 bytes x 2 entries)

• Mixed 256-Kbyte cache for instructions and data
• 32-byte block length
• Write-through mode

• Three independent read/write ports
  • Instruction fetch access by the CPU
  • 8-/16-/32-bit operand access by the CPU
  • 8-/16-/32-/64-bit and 16-/32-byte access by the SuperHyway bus master
• 16K-byte capacity

• High-performance on-chip 64-bit-width system bus accessed with 32-bit addresses
• Packet router (GPR) controls transfer between the initiator and target
• Initiator modules: SH-x2, DBG, DMAC, ICB, 2DG, ATAPI, EtherMAC, and SPU
• Dynamically controls the priority among initiators
  Normal transfer: Complete LRU control
  Urgent transfer: Desired priority level can be set for the target initiator

• On-chip RAM accessible from the CPU and SuperHyway bus master
• Data retention in R-standby mode
• 2-Kbyte capacity
• Can be used to store the program for returning from R-standby mode

• Nine independent external interrupts (NMI and IRQ7 to IRQ0)
  • NMI: Falling or rising edge selectable
  • IRQ: Falling or rising edge or high or low level selectable
• On-chip module interrupts: Priority can be set for each module
  The following modules can issue on-chip module interrupts
  DMAC, ATAPI, TPU, TMU, CMT, MSIOF, SCIF, SCIFA, RTC, IrDA, KEYSC, USB, IIC, MMCIF, VPU, VIO5 (CEU, VEU, BEU), 2DG, LCDC, VOU, JPU, ICB, 2DDMAC, TSIF, FSI, SPU, EtherMAC, and SDHI

Bus state controller
(BSC)

• Provides SRAM, burst ROM, and PCMCIA interface functions
• Supports external address space up to 256 Mbytes in total. The space can be divided into areas in either of the following two ways.
  • Address map 1: Six areas (areas 0, 4, 5A, 5B, 6A, and 6B)
  • Address map 2: Four areas (areas 0, 4, 5, and 6)
• The following parameters can be specified for each area
  • Memory type: SRAM, NOR-flash memory, burst ROM, PCMCIA
  • Data bus width: 8, 16, or 32 bits selectable (only 16 or 32 bits for area 0)
  • Number of wait cycles

• DDR2-SDRAM or Mobile DDR-SDRAM can be directly connected
• Up to 512-Mbyte physical address space
• 32- or 16-bit data bus width
• Supports auto-refresh and self-refresh modes
• Number of banks: 4 or 8 banks (DDR2) or 4 banks (Mobile-DDR)
  Note that up to four banks can be opened together in 8-bank mode.
• Burst length: Fixed at 4
• Burst type: Sequential
• CAS latency: Fixed at 3
• Power-down mode
• Deep power-down mode (only for Mobile-DDR)
• Partial self-refresh mode (only for Mobile-DDR)
• Auto-precharge mode or bank active mode

Direct memory access controller
(DMAC)

• Twelve channels; two channels accept external requests
• Address space: 4 Gbytes on architecture
• Data transfer length: Bytes, words (2 bytes), longwords (4 bytes), 16 bytes, and 32 bytes
• Maximum number of transfer times: 16,777,216 times
• Addressing mode: Dual addressing mode
  Transfer request selectable from three types: External request, on-chip peripheral module request, and auto request
• On-chip peripheral module requests can be issued from the following:
  SCIF, SCIFA, MSIOF, SDHI, TSIF, IrDA, USB, and MMCIF
• Bus mode: Cycle steal mode (normal mode and intermittent mode) or burst mode is selectable
• Priority: Fixed channel priority mode or round-robin mode is selectable
• Interrupt request: Supports the interrupt request to CPU at the end of data transfer
• Repeat function: Automatically resets the transfer source, destination, and count at the end of DMA transfer
• Reload function: Automatically resets the transfer source and destination at the end of the specified number of DMA transfers

• Three types of clock source selectable
  • EXTAL pin input: 10 MHz to 66.7 MHz
  • RTC_CLK pin input: 32.768 KHz. RTC operating clock.
  This clock can be multiplied up to the order of MHz through the FLL circuit as the `system clock source.
  • Crystal resonator: Connect to the EXTAL and XTAL pins
• Generates four types of system clocks
  • CPU clock (IΦ): 500 MHz max.
  • SuperHyway/DDR clock (SΦ): 166.7 MHz max. (DDR333 is supported)
  • Bus clock (BΦ): 83.4 MHz max.
  • Peripheral clock (PΦ): 41.7 MHz max.
• Generates specialized clocks for peripheral modules
  • M1Φ: Operating clock for the VPU. 166.7 MHz max.
  • RCLK: RWDT and CMT operating clock
  • FSICK: FSI interface clock
• Dynamic control of the system clock frequency through modification of PLL multiplication or division ratio by software
• Supports power-down modes
  • Module standby mode (stops the clock in module units)
  • Sleep mode (stops the clock for the CPU core)
  • Software standby mode (stops the clock inside the LSI except the I/O block and RCLK operation area)
• R-standby mode (stops the power supply inside the LSI except RCLK operation area, RS memory, and some registers)
  • U-standby mode (stops the power supply inside the LSI except the I/O block and RCLK operation area)

• One-channel watchdog timer operating on RCLK
• Can operate in power-down modes
• Generates a system reset at a counter overflow

• On-chip 6-channel 32-bit timer
• Auto-reload-type 32-bit down counter
• Internal prescaler for PΦ

• On-chip 4-channel 16-bit timer
• Four pulse signals can be output
• Up to 4-phase PWM output is available

• On-chip 1-channel 32-bit timer (16 bits or 32 bits selectable)
• Source clock: RCLK
• Compare match function

• On-chip clock and calendar functions operating on RTC_CLK
• Generates alarm and peripheral interrupts

• Two channels
• Separate internal 64-byte FIFOs for transmission and reception
• Clocked synchronous serial master and slave modes. Full-duplex communication supported.
  • Supports 8-/16-bit data and 16-bit stereo audio input/output
  • Supports 24-bit stereo audio input/output
  • Sampling rate clock input selectable from BΦ and external pin
  • Internal prescaler for BΦ
• SPI master and slave modes. Full-duplex communication supported.
  • Serial clock (SCK) falling or rising edge selectable for data sampling timing
  • SCK clock phase selectable for transmit timing. Three slave devices selectable.
  • Transmit/receive data length selectable from 8 bits, 16 bits, and 32 bits

• Three channels (SCIF0 to SCIF2)
• Separate internal 16-byte FIFOs (8 bits x 16 FIFOs) for transmission and reception
• Supports asynchronous mode and clocked synchronous mode (master/slave)
• High-speed UART for Bluetooth
• Internal prescaler for PΦ

Serial communication interface with FIFO
(SCIFA)

• Three channels (SCIFA3 to SCIFA5)
• Separate internal 64-byte FIFOs (8 bits x 64 FIFOs) for transmission and reception
• Supports asynchronous mode and clocked synchronous mode (master/slave)
• Modem control function (RTS, CTS) (only in SCIF3)
• High-speed UART for Bluetooth
• Internal prescaler for BΦ

• Conforms to version 1.2a
• CRC generation function

• Key scan: Chattering elimination in key input interrupt detection
  Number of input or output bits is selectable (5 inputs/6 outputs, 6 inputs/5 outputs, or 7 inputs/4 outputs)
  Software standby, R-standby, and U-standby modes can be canceled by a key input

• Supports primary channel
• Master and slave functions
• Supports PIO modes 0 to 4, multiword DMA modes 0 to 2, and Ultra DMA modes 0 to 4
• Supports descriptor mode
• 3.3-V I/O interface

• On-chip USB2.0 host controller and function controller
• Two channels of USB host controller and function controller can be switched through register settings
• Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transfer
• Internal USB transceiver
• Supports all USB transfer types
• Control, bulk, interrupt (high bandwidth not supported), and isochronous (high bandwidth not supported) transfer
• Up to eight pipes selectable (including the default control pipe)
• Desired endpoint numbers can be assigned to pipes 1 to 7
• Transfer type selectable for each pipe
• Pipe 0: Control transfer
• Pipes 1 and 2: Bulk or isochronous transfer
• Pipes 3 to 5: Bulk transfer
• Pipes 6 and 7: Interrupt transfer
• Input EXTALUSB clock: 48 MHz

• Two channels (IIC0 and IIC1)
• Supports single master transmission and reception
• Supports standard mode (100 kHz) and fast mode (400 kHz)

• The incorporated multi-codec (VPU5F) handles various moving-picture formats.
  MPEG-4 single video object plane (VPO) encoding and decoding
• Applicable standard
  MPEG-4 Simple Profile
  MPEG-4 H.264 (Baseline) *1
  JPEG Baseline (VLC requires software processing)
  WMV Simple Profile MainProfile*2
  Notes: 1. Some Baseline tools are not supported.
  2. Some tools (Dynamic Resolution Change, B-Frame, and Range Reduction) are not supported
• Image size: Sub-QCIF to XGA and HD (1280 x 720) supported
• Bit rate: 8 Mbps max.
• Motion detection: Layer tracking (Renesas Electronics original method)
• Rate control: Control with quantizing amount predicted (Renesas Electronics original method), both VOP and MB supported

Consists of the following three modules that provide the interface with the camera module and perform image processing

• CEU (capturing engine: image capturing from camera module)
  • Two channels (supports two cameras)
  • Camera module interface
  YCbCr data (8 or 16 bits: YCbCr 4:2:2), horizontal sync signal (HD), vertical sync signal (VD), and binary data (such as RGB565)
• Size of captured image: 5-M pixels, 3-M pixels, 2-M pixels, UXGA, SXGA, XGA, SVGA, VGA, CIF, QVGA, QCIF, QQVGA, Sub-QCIF
  • Output image format: YCbCr (4:2:2/4:2:0)
  • Image format conversion function
  Reduced image generating prefilter function
  YCbCr 4:2:2→ YCbCr 4:2:2, YCbCr 4:2:0
  YCbCr format (Y: 8 bits; CbCr: 16 bits)
• VEU3F (video engine: image processing in memory)
  • Two channels
  • Video image processing function
  Input image format: YCbCr image (Y/CbCr plane image), RGB image (packed RGB image)
  Output image format: YCbCr image (Y/CbCr plane image), RGB image (packed RGB image)
  • Image processing function
  Scaled image generating filter function
  YCbCr → RGB and RGB → YCbCr conversion function
  Dithering function (in RGB color subtraction)
• Filter processing function
  Mirroring, vertical inversion, point symmetry, and ?90-degree image conversion functions
  Deblocking filter
  Median filter
  • Video image processing and filter processing combined operation
• BEU2G (blend engine: image blending)
• Two channels (supports simultaneous two-plane output)
• PinP function
  Input image format: YCbCr image (Y/CbCr plane image), RGB image (packed RGB image)
  Output image format: YCbCr image (Y/CbCr plane image), RGB image (packed RGB image)
• Graphic processing function
  Input graphic format: YCbCr/RGB image
  Output graphic format: YCbCr/RGB image
  • PinP and graphic combined operation
  Two PinP planes and one graphic plane can be blended simultaneously
• Results of processing are written back to memory
• Frame drop function (1/2, 1/3, 1/4, 1/5, or 1/6 drop)

• Drawing functions
  Four-vertex drawing, polygon drawing, line drawing, high-functional bold line drawing, antialiasing, raster operation/BitBLT with alpha blending
• Color representation
  • Source: 1, 8, or 16 bits/pixel
  • Drawing: 8 or 16 bits/pixel
  • Work: Binary
• Screen coordinates
  • X direction: 0 to 4095
  • Y direction: 0 to 4095

LCD controller
(LCDC)

• LCD panel: TFT color LCD, up to SXGA supported
• Input data format: 12, 16, 18, or 24 bpp
• LCD driver interface
  • Specialized LCD bus, independent of memory bus
  • RGB interface or 80-series CPU bus interface selectable
  • Bus width: 8, 9, 12, 16, 18, and 24 bits supported
  • One-pixel one-time, two-time, and three-time transfer modes supported
  • Signal polarity and SYNC output position and width programmable in RGB interface
  • Access cycle programmable in 80-series CPU bus interface
• Dot clock: Bus clock, peripheral clock, or external clock selectable as the source clock
• Display data fetch: Continuous mode (according to the refresh rate of the LCD panel) and one-shot mode (according to the frame rate of the movie) are supported. Image data only for updated sections can be fetched selectively.
• Internal 256-entry, 24-bit-input/output color palette
• An interrupt can be generated in frame units or at the user-specified line.

• Output format: Conforms to ITU-R BT.601 and ITU-R BT.656
• Output interface: Supports 16-bit Y/C separate interface and 8-bit Y/C composite interface
• Pixel frequency: 13.5 MHz (for 16-bit interface) or 27 MHz (for 8-bit interface)
• Partial image display: Any background color (specified through register) + display image
• Supported image size: Sub-QCIF, QVGA, VGA, etc.

• Applicable standard: JPEG baseline
• Operating precision: Conforms to JPEG Part 2, ISO-IEC10918-2
• Color format: YCbCr (4:2:2/4:2:0)
• Quantization tables: Four tables provided
• Huffman tables: Four tables provided (two AC tables and two DC tables)
• Target markers: SOI, SOF0, SOS, DQT, DHT, DRI, RSTm, EOI

• 128 Kbytes
• Line buffer control function of maximum 32 planes
• Can be used as the read fill buffer or write back buffer of the corresponding IP
• Can be used as the middle buffer between corresponding IPs
• Part of the frame buffer data for the LCDC is cacheable

• Two YCbCr planes and four RGB planes can be processed
• Supports image clipping in 1-pixel units for RGB and 2-pixel units for YCbCr
• Conversion between various RGB formats
• Images can be scaled up twice respectively in the X direction and the Y direction
• Vertical and horizontal inversion and 90℃ and 270℃ rotation

• Serial TS data input
• Filters 38 types of PIDs in total
  (Note that the PID values of PAT and CAT packets are fixed. For PCR, video, and audio packets, the PID values are predefined.)

• 24-bit stereo
• Supports PCM and I2S formats
• Two sound input systems and two sound output systems
• Serial I/O can be directly connected to external A/D and D/A converters
• Can be directly connected to the SPU

• Two internal audio DSPs (24-bit dual MAC)
• DMA function available
• Internal 160-Kbyte RAM for programs and 264-Kbyte RAM for data

Ethernet controller
(EtherMAC)

• Ethernet controller conforming to the Ethernet media access control (MAC) layer standard
  • Transmission and reception of Ethernet/IEEE802.3 frames
  • 10-Mbps and 100-Mbps transfer
  • Full-duplex and half-duplex modes
  • Reduced media independent interface (RMII)
  • Flow control conforming to the IEEE802.3x standard
• Specialized DMA controller
  • Reduces the load on the CPU by means of a descriptor management system
  • Reflects transmit/receive frame status on the descriptor
  • Achieves efficient system bus utilization through block (32-byte) transfer
  • Supports single-frame multi-buffer transfer
  • Improves the software processing performance through padding in received data

• Provides Multi Media Card (MMC) and CE-ATA device control functions
• Data bus: 1-bit, 4-bit, and 8-bit MMC modes supported (SPI mode not supported)
• Supports block transfer (stream transfer not supported)
• Block size for multi-block transfer: 512 bytes
• Supports the command completion signal (CE-ATA)
• NAND boot function conforming to MMC4.2

• Two channels
• Supports SD memory and SDIO card interface
• Card detecting function
• Maximum operating frequency: 50 MHz (high speed supported)

• Input or output can be selected for each input/output port independently

• Provides user-break interrupts for debugging
• Two break channels
• Addresses, data values, access types, and data sizes are all specifiable as break conditions
• Provides sequential break functions

• Supports E10A emulator
• Realtime branch trace functions